Journals
Journals: (119)
2023 (13)
120. Vishwakarma, S., Raut, G., Jaiswal, S., Vishvakarma, S. K., & Ghai, D. (2024). A Precision-Aware Neuron Engine for DNN Accelerators. SN Computer Science, 5(5), 494. [PDF]
119.Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, and Akash Kumar, "QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit," in IEEE Access, doi: 10.1109/ACCESS.2024.3379906.
118. Narendra Singh Dhakad, Eshika Chittora, Vishal Sharma, Santosh Kumar Vishvakarma, “R-InMAC: 10T SRAM based Reconfigurable and Efficient In-Memory Advance Computation for Edge Devices,” Analog Integrated Circuits and Signal Processing, Springer, August 2023. [PDF]
117. Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma, "In-Memory Computing with 6T SRAM for Multi-Operator Logic Design", Circuits, Systems, and Signal Processing (CSSP), Springer, August 2023. [PDF]
116. Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma, "Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs", Circuits, Systems, and Signal Processing (CSSP), Springer, August 2023. [PDF]
115. Megha Nawaria, Sanjay Kumar, Mohit Kumar Gautam, Narendra Singh Dhakad, Rohit Singh, Sonal Singhal, Pawan Kumar, Santosh Kumar Vishvakarma and Shaibal Mukherjee, "Memristor-inspired Digital Logic Circuits and Comparison with 90-/180-nm CMOS Technologies", IEEE Transactions on Electron Devices, June 2023. [PDF]
114. Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma, "Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators," Circuits, Systems, and Signal Processing (CSSP), Springer, May 2023. [PDF]
113. Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma, "An Empirical Approach to Enhance Performance for CORDIC-based Deep Neural Networks", ACM Transactions on Reconfigurable Technology and Systems, May 2023. [PDF]
112. Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma, "Clock Gating-based Effectual Realization of Stochastic Hyperbolic Tangent function for Deep Neural Hardware Accelerators," Circuits, Systems & Signal Processing (CSSP), Springer, May 2023. [PDF]
111. Sumiran Mehra, Gopal Raut, Ribhu Das Purkayastha, Santosh Kumar Vishvakarma, Anton Biasizzo, "An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning," IEEE Access, Volume 11, April 2023. [PDF]
110. Deepika Gupta, Abhishek Kumar Upadhyay, Ankur Beohar, Santosh Kumar Vishvakarma, "Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping", Memories - Materials, Devices, Circuits and Systems, Elsevier, Volume 4, July 2023. [PDF]
109. Priyanka Sharma, Vaibhav Neema, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, "MPEG/H256 Video Encoder with 6T/8T Hybrid Memory Architecture for High Quality Output at Lower Supply", Memories - Materials, Devices, Circuits and Systems, Elsevier, Volume 4, July 2023. [PDF]
108. Bharath Sreenivasulu Vakkalakula, Aruna Neelam, Lokesh Vakkalakula, Santosh Kumar Vishvakarma, Vadthiya, Narendar, “Common Source Amplifier and Ring Oscillator Performance Optimization Using Multi-Bridge/Nanosheet FETs", ECS Journal of Solid State Science and Technology, The Electrochemical Society, IOP Science, Volume 12, February 2023. [PDF]
107. Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma, "Enabling Energy-Efficient In-Memory Computing with Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 13, March 2023. [PDF]
2022 (08)
106. Ravi Kumar, Pooja Bohara, Krishna Thakur, S K Vishvakarma, “A 5.5 GHz 1.9 mW Low Power 8/9 Dual Modulus Divider in 180nm CMOS Technology”, Journal of Circuits, Systems, and Computers, World Scientific, August 2022. [PDF].
105. Ravi Kumar, Rajasekhar Nagulapalli, S K Vishvakarma, “A Novel Bias Circuit Technique to Reduce the PVT variations in Ring Oscillator using 65nm CMOS Technology”, Journal of Circuits, Systems, and Computers, World Scientific, August 2022. [PDF]
104. Gopal Raut, Anton Biasizzo, Narendra Singh Dhakad, Neha Gupta, Gregor Papa, Santosh Kumar Vishvakarma, “Data Multiplexed and Hardware Reused Architecture for Deep Neural Network Accelerator”, Neurocomputing, Elsevier, Volume 486, 14 May 2022, Pages 147-159. [PDF]
103. Gunjan Rajput, Kunika Naresh Biyani, V Logashree, Santosh Kumar Vishvakarma, “SCAN: Streamlined Composite Activation-function-unit for Deep Neural Accelerators”, Circuits, Systems & Signal Processing (CSSP), Springer, February 2022. [PDF]
102. Gunjan Rajput, Sashank Agrawal, Kunika Naresh Biyani, Santosh Kumar Vishvakarma, “Early Breast Cancer Diagnosis using Cogent Activation Function-based Deep learning implementation on screened mammograms”, International Journal of Imaging Systems and Technology, Wiley, January 2022. [PDF]
101. Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma, “BitMAC: Bit-Serial Computation based Efficient Multiply-Accumulate Unit for DNN Accelerator”, Circuits, Systems & Signal Processing (CSSP), Springer, Volume 41, Pages 2045-2060, April 2022. [PDF]
100. Pooja Bohara and Santosh Kumar Vishvakarma, “Overcoming Bit Loss Mechanism in Self-Amplified Multi-Level SONOS Memory Cell”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, Volume 35, Issue 1, Article 2924, January 2022. [PDF]
99. Gunjan Rajput, Sashank Agrawal, Gopal Raut and Santosh Kumar Vishvakarma, “An Accurate and Non-Invasive Screening of Skin Cancer Based on the Imaging Technique”, International Journal of Imaging System and Technology, Wiley, Volume 32, Issue 1, Page 354-368, January 2022. [PDF]
2021 (12)
98. Natwar Bhootda, Ankit Yadav, Vaibhav Neema, Ambika Prasad Shah and Santosh Kumar Vishvakarma, “Series Diode-connected Current Mirror based Linear and Sensitive NBTI Monitoring Circuit”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, Volume 35, Issue 2, September 2021. [PDF]
97. Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J., Srinivas M. B., Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi, “Classification of Targets using Statistical Features from Range FFT of mmWave FMCW Radars”, Electronics, MDPI, Volume 10, Issue 16, August 2021. [PDF]
96. Neha Gupta, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl, Patrick Girard, “Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications”, Electronics, MDPI, Volume 10, Issue 14, July 2021. [PDF]
95. Gunjan Rajput, Gopal Raut, Mahesh Chandra, and Santosh Kumar Vishvakarma, “VLSI implementation of Transcendental Function-Hyperbolic Tangent for a Neural Network Accelerators”, Microprocessor and Microsystem, Elsevier, Volume 84, July 2021. [PDF]
94. Swati Mishra, Santhakumar Mohan and Santosh Kumar Vishvakarma, “Performance Investigations of an Improved Backstepping Operational-space Position Tracking Control of a Mobile Manipulator”, Defence Science Journal, Volume 71, No. 4, July 2021. [PDF]
93. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Vishwakarma and Akash Kumar, “A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies”, IEEE Access, Volume 9, Page 91564-91574, June 2021. [PDF]
92. Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Jai Gopal Pandey, and Santosh Kumar Vishvakarma, “A D Flip-flop based TRNG with Zero Hardware Cost for IoT Security Applications”, Elsevier, Microelectronics Reliability, Volume 120, May 2021. [PDF]
91. Vaibhav Neema, Mansimran Kaur, Deepika Gupta, Santosh Kumar Vishvakarma, Arya Dutt and Ankur Beohar, “Improvement in Electrical Characteristics of BE-SONOS Using High-k Dielectrics in Tunneling Barrier”, Transaction on Electrical and Electronic Material, March 2021. [PDF]
90. Neha Gupta, Ambika Prasad Shah, and Santosh Kumar Vishvakarma. “BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit”, IEEE Transactions on Device and Materials Reliability, Volume 21, Issue 1, March 2021. [PDF]
89. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, and Akash Kumar. “RECON: Resource-efficient CORDIC-based neuron architecture”, IEEE Open Journal of Circuits and Systems, Page no. 170-181, February 2021. [PDF]
88. Neha Gupta, Ambika Prasad Shah, Rana Sagar Kumar, Gopal Raut, Narendra Singh Dhakad, and Santosh Kumar Vishvakarma, “Soft Error Hardened Voltage Bootstrapped Schmitt Trigger Design for Reliable Circuits” Microelectronics Reliability, Elsevier, Volume 117, February 2021. [PDF]
87. Vishal Sharma, Neha Gupta, Ambika Prasad Shah, Santosh Kumar Vishvakarma & Shailesh Singh Chouhan, “A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes”, Analog Integrated Circuits and Signal Processing, 107, pages 339–352(2021). [PDF]
2020 (09)
86. Mahesh Kumawat, Abhishek K. Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh and S.K. Vishvakarma, “ An Improved Current Mode Logic Latch for High-Speed Applications “, International Journal of Communication Systems, Wiley, Volume 33, Issue 13, Sep 2020. [IF 1.319]
85. Neha Gupta, Ambika Prasad Shah, Rana Sagar Kumar, Sajid Khan, and Santosh Kumar Vishvakarma, “On Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell with Improved Soft Error Tolerance”, IEEE Transactions on Device and Materials Reliability, Aug. 2020. [PDF]
84. Mahesh Kumawat, Mohit S. Choudhary, Ravi Kumar, Gaurav Singh and S. K. Vishvakarma, “A Novel CML Latch Based Wave Pipelined Asynchronous SerDes Transceiver for Low Power Application”, Journal of Circuits, Systems, and Computers, World Scientific, Volume 29, Issue 7, June 2020. [IF 1.363]
83. Neha Gupta, Vishal Sharma, Ambika Prasad Shah, Sajid Khan, Michael Huebner, Santosh Kumar Vishvakarma, “An Energy-Efficient Data-Dependent Low-Power 10T SRAM Cell Design for LiFi Enabled Smart Street Lighting System Application,” International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, Willey, pp. 2766, volume 33, issue 6, June 2020. [PDF]
82. Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Sudha Rani, Neha Gupta, Jai Gopal Pandey, Santosh Kumar Vishvakarma, “Utilizing Manufacturing Variations to Design A Tri-State Flip-flop PUF for IoT Security Applications,” Analog Integrated Circuits and Signal Processing, Springer, April 2020. [PDF]
81. Ambika Prasad Shah, Daniele Rossi, Vishal Sharma, Santosh Kumar Vishvakarma, and Michael Waltl, “Soft Error Hardening Enhancement Analysis of NBTI Tolerant Schmitt Trigger Circuit”, Microelectronics Reliability, Elsevier, vol. 107, pp. 113617, April 2020. [PDF]
80. Ambika Prasad Shah, Santosh Kumar Vishvakarma, and Michael Huebner, “Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications”, Springer Journal of Electronic Testing: Theory and Applications, vol. 36, no. 2, pp. 1-11, April 2020. [PDF]
79. Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Neha Gupta, Jai Gopal Pandey, and Santosh Kumar Vishvakarma, "A Symmetric D flip-flop based PUF with improved uniqueness", Elsevier, Microelectronics Reliability, vol. 106, pp. 113595, March 2020. [PDF]
78. Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, and Santosh Kumar Vishvakarma, "A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture", Springer, Circuits, Systems, and Signal Processing, pp. 1-14, Feb. 2020. [PDF]
77. Vivek Pogra, Santosh Kumar Vishvakarma, Balwinder Raj, "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application, " Sensor Letters, ASP, Vol. 18, No. 1, pp. 31-38(8), January 2020. [PDF]
76. Swati Mishra, Santhakumar Mohan and Santosh Kumar Vishvakarma, "Simplified Motion Control of a Vehicle Manipulator for the Coordinated Mobile Manipulation," Defense Science Journal, Vol. 70, No.1, pp. 72-81, Jan 2020. [PDF]
2019 (11)
75. Ambika Prasad Shah, Santosh Kumar Vishvakarma and Sorin Cotofana, “NBTI Stress Delay Sensitivity Analysis of Reliability Enhanced Schmitt Trigger-based Circuits”, Elsevier, Microelectronics Reliability, Volume 102, November 2019. [PDF]
74. Prachi Sanvale, Neha Gupta, Vaibhav Neema, Ambika Prasad Shah, Santosh Kumar Vishvakarma, “An improved read-assist-energy efficient single-ended P-P-N based 10T SRAM cell for wireless sensor network,” Microelectronics Journal, Elsevier, Volume 92, October 2019. [PDF]
73. Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, and Santosh Kumar Vishvakarma, ”An Ultra-Lightweight Low Power Reconfigurable NBTI Resilient RO-PUF for IoT Applications”, Microelectronics Journal, Elsevier, Volume 92, October 2019. [PDF]
72. Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma, "A Novel CML Latch Based Wave Pipelined Asynchronous SerDes Transceiver for Low Power Application", Journal of Circuits, Systems, and Computers, World Scientific, Volume 29, No. 7. [PDF]
71. Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh, and Santosh Kumar Vishvakarma, “An Improved Current Mode Logic Latch for High-Speed Applications”, International Journal of Communication System Wiley, July 2019. [PDF]
70. Deepika Gupta and Santosh Kumar Vishvakarma, “Effect of Spacer Dielectric on the Program Disturb of 3-D Junction-Free NAND Flash Memory,” Journal of Nanoelectronics and Optoelectronics (JNO) ASP, Volume 14, Number 6, pp. 812-817(6), June 2019. [PDF]
69. Vaibhav Neema, Kuldeep Raghuvanshi, Ambika Prasad Shah and Santosh Kumar Vishvakarma, “Vth Extraction based Run Time Transistor Width Oversizing (TWOS) Module for On-chip Negative Bias Temperature Instability (NBTI) Mitigation, Sensor Letters, vol. 17, May 2019, pp. 385-392(8). [PDF].
68. Vishal Sharma, Prashu Bisht, Abhishek Dalal, Maisagalla Gopal, Santosh Kumar Vishvakarma, and Shailesh Singh Chouhan, “Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications”, International Journal of Electronics and Communications, Elsevier, Vol. 104, pp. 10-22, May 2019. [PDF]
67. Ambika Prasad Shah and Santosh Kumar Vishvakarma, “An Energy-Efficient 8-Transistor Full Adder Cell-Based on Degenerate Pass Transistor Logic”, IEEE VLSI Circuits and Systems Letter, Vol. 5, No. 2, pp. 1-6, May 2019. [PDF]
66. Mahesh Kumawat, Abhishek Dalal, Mohit S. Chaudhary, Ravi Kumar, Gaurav Singh and Santosh Kumar Vishvakarma, "Wave Combining Driver based Serial Data Link Transceiver Design for Multi-Standard Applications," Journal of Nanoelectronics and Optoelectronics (JNO), ASP, Volume 14, Number 5, pp. 675-679(5), May 2019. [PDF]
65. Pooja Bohara and Santosh Kumar Vishvakarma, "NAND Flash Memory Device with Ground Plane in Buried Oxide for Reduced Short Channel Effects and Improved Data Retention," Journal of Computational Electronics, Springer, Issues 2, Jan 2019. [PDF]
2018 (22)
64. R. R. Sharma, P. Varshney, R.B. Pachori, and Santosh Kumar Vishvakarma, "Automated system for epileptic EEG detection using iterative filtering", IEEE Sensors Letters, Volume: 2, Issue: 4, Dec. 2018. [PDF]
63. Nandakishor Yadav, Ambika Prasad Shah, Ankur Beohar and Santosh Kumar Vishvakarma, “Symmetric dual Gate Insulator based FinFET Module and Design Window for Reliable Circuits”, IET Micro Nano Letters, Nov 2018. [PDF]
62. Abhishek Upadhyay, Ajay Kushwaha, Priyank Rastogi, Yogesh Chauhan, and Santosh Kumar Vishvakarma, “Explicit Model of Channel Charge, Backscattering and Mobility for Graphene FET in Quasi-Ballistic Regime,” IEEE Transactions on Electron Devices, Vol. 65, issues 12, pp. 5468 - 5474, December 2018. [PDF]
61. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma, "SUBHDIP: Process Variations Tolerant Subthreshold Darlington Pair Based NBTI Sensor Circuit," IET Computers & Digital Techniques, Sept 2018. [PDF]
60. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar and Santosh Kumar Vishvakarma, “Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits,” IEEE Transactions on Device and Materials Reliability, vol. 16, issue 4, pp. 546-554, Dec 2018. [PDF]
59. Pooja Bohara and Santosh Kumar Vishvakarma, "Self-Amplified Tunneling Based SONOS Flash Memory Device with Improved Performance", IEEE Transactions on Electron Devices, vol. 65, issues 19, pp. 4297 - 4303, Aug 2018. [PDF]
58. Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh Reniwal, Nandkishor Yadav, Santosh Kumar Vishvakarma and Devesh Dwivedi, "An Auto Calibrated Sense Amplifier with Offset Prediction Approach for Energy Efficient SRAM, "Circuits, Systems & Signal Processing (CSSP), Springer, Aug. 2018. [PDF]
57. Vishal Sharma, Maisagalla Gopal, Pooran Singh, S. K. Vishvakarma and Shailesh Singh Chouhan, “A Robust, Ultra Low-Power, Data-Dependent-Power-Supplied 11T SRAM Cell with Expanded Read/Write Stabilities for Internet-of-Things Applications,” Analog Integrated Circuits and Signal Processing, Springer, pp 1-16, Aug, 2018. [PDF]
56. Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan and Kari Halonen, “A Write-Improved Low-Power 12T SRAM Cell for Wearable Wireless Sensor Nodes" International Journal of Circuit Theory and Applications, Wiley, Aug, 2018. [PDF]
55. Ankur Beohar, Nandakishor Yadav, Ambika Prasad Shah, and Santosh Kumar Vishvakarma, "Analog/RF attributes of 3D-Cyl underlap GAA-TFET based on Ge-Source using fringing field engineering for low power applications, " Journal of Computational Electronics, Springer, July 2018. [PDF]
54. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma, "An Efficient NBTI Sensor and Compensation Circuit for Stable and Reliable SRAM Cells," Microelectronics Reliability, Elsevier, Vol. 87, pp 15-23, August 2018. [PDF]
53. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar and Santosh Kumar Vishvakarma, "NMOS Only Schmitt Trigger Circuit for NBTI Resilient CMOS Circuits," IET Electronics Letter, Vol. 54 No. 14 pp. 868–870, July 2018. [PDF]
52. Maisagalla Gopal, Atul Awadhiya, Nandakishor Yadav, Santosh Kumar Vishvakarma and Vaibhav Neema, “Impact of Varying Carbon Concentration in SiC S/D Asymmetric Dual-k Spacer for High Performance and Reliable FinFET", Journal of Semiconductors, Vol 35, Issues 10, October 2018. [PDF]
51. Pooran Singh and Santosh Kumar Vishvakarma, "Ultra Low Power-High Stability, Positive Feedback Controlled (PFC) 10T SRAM cell for Lookup Table (LUT) Design, "Integration, the VLSI Journal, vol 62, pp 1-13, June 2018. [PDF]
50. Divya Yadav, Shailesh Singh Chouhan, Santosh Kumar Vishvakarma and Balwinder Raj, "Application Specific Microcontroller Design for IoT based WSN”, Sensor Letter, American Scientific Publishers, USA, vol. 16, no. 5, pp. 374–385, May 2018. [PDF]
49. Vishal Sharma, Maisagalla Gopal, Pooran Singh, and Santosh Kumar Vishvakarma, “A 220 mV Robust Read-Decoupled Partial Feedback Cutting based Low-Leakage 9T SRAM for Internet of Things (IoT) Applications,” International Journal of Electronics and Communications, Elsevier, vol. 87, pp. 144-157, April 2018. [PDF]
48. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, and Santosh Kumar Vishvakarma, “On-chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells,” IEEE Transactions on Semiconductor Manufacturing, vol. 31, issue 2, pp. 242-249, May 2018. [PDF]
47. Pooran Singh and Santosh Kumar Vishvakarma, " Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System", IEEE Access, Vol. 6, pp. 2279 - 2290, 2018. [PDF]
46. Abhishek Upadhyay, Ajay Kushwaha and Santosh Kumar Vishvakarma, "A Unified Scalable Quasi-Ballistic Transport Model of GFET for Circuit Simulations", IEEE Transactions on Electron Devices, issues 2, Vol. 65, pp. 739 - 746, Feb. 2018. [PDF]
45. Maisagalla Gopal, Vishal Sharma, and Santosh Kumar Vishvakarma, "SiGe Asymmetric Dual-k Spacer FinFETs-based 6T SRAM Cell to Mitigate Read-Write Conflict", Journal of Nanoelectronics and Optoelectronics (JNO), ASP, vol. 13, no. 4, pp 467-471, April 2018. [PDF]
44. Shraddha Singh, S. K. Vishvakarma and Balwinder Raj, "Analytical Modeling of Split-Gate Junction-Less Transistor for a Biosensor Application”, Sensing and Bio-sensing, Elsevier, vol. 18, pp. 31-36, April 2018. [PDF]
43. S. Mishra, P.S Londhe, M. Santhakumar, S.K. Vishvakarma, B.M Patre, “Task space motion control of a mobile manipulator using a nonlinear PID control along with an uncertainty estimator" in Special issue on Advancements in Automation, Robotics and Sensing - Computers and Electrical Engineering by Elsevier - An International Journal, Vol. 67, pp. 729-740, April 2018. [PDF]
2017 (11)
42. Pooran Singh and S. K. Vishvakarma, “Ultra low power process tolerant 10T (PT10T) SRAM with improved read/write ability for internet of things (IoT) applications," Journal of Low Power Electronics and Applications, vol. 7, no. 3, 24, pp. 1-22, Sept. 2017. [PDF]
41. Maisagalla Gopal, Vishal Sharma and Santosh Kumar Vishvakarma, "Evaluation of Static Noise Margin (SNM) of 6T SRAM Cell using SiGe/SiC Asymmetric Dual-k Spacer FinFETs", IET Micro & Nano Letters, Vol. 12, Issues 12, pp. 1028-1032, December 2017. [PDF]
40. Abhishek Upadhyay, Nitesh Chauhan and S.K.Vishvakarma, "A Compact Electrical Modeling for Top-Gated Doped Graphene Field-Effect Transistor", IETE Journal of Research, Taylor & Francis, Aug. 2017. [PDF]
39. Ankur Beohar, Nand Kishor Yadav and Santosh Kumar Vishvakarma, "Analysis of trap assisted tunneling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability," IET Micro & Nano Letters, Vol. 12, Issues 12, pp. 982-986, December 2017. [PDF]
38. Pooran Singh and S. K. Vishvakarma “Low Complexity-Low Power Object Tracking Using Dynamic Quad-tree Pixelation and Macro-block Resizing,” Pattern Recognition and Image Analysis, Springer, vol 27, issue 4, pp 731-739, Oct 2017. [PDF]
37. Nandakishor Yadav, Ambika Prasad Shah and Santosh Kumar Vishvakarma, "Stable, Reliable and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-design," IEEE Transactions on Semiconductor Manufacturing, issue 99, June 2017. [PDF]
36. Vikas Vijayvargiya, Bhupendra Reniwal, Pooran Singh, Santosh Kumar Vishvakarma, "Impact of Device Engineering on Analog/RF Performances of Tunnel Field Effect Transistor", Semiconductor Science and Technology, IOP Science, Vol 32, No. 6, May 2017. [PDF]
35. Pooran Singh, B. S. Reniwal, V. Vijayvargiya, Vishal Sharma and S. K. Vishvakarma," Dynamic Feedback-Controlled Static Random Access Memory for Low Power Applications", Journal of Low Power Electronics, Vol. 13, No. 1, pp. 47-59 (13), March 2017, ASP, USA. [PDF]
34. S. K. Vishvakarma, Ankur Beohar, Vikas Vijayvargiya and Priyal Trivedi, "Analysis of DC and Analog/RF performance on Cyl-GAA-TFET using distinct device Geometry", Journal of Semiconductors, IOPscience, vol. 38, no. 7, pp. 074003- 1-5, July 2017. [PDF]
33. Deepika Gupta and S. K. Vishvakarma, "Improvement of Short Channel Performance of Junction-Free Charge Trapping 3D NAND Flash Memory " IET Micro & Nano Letters, Vol. 12, Issues 1, pp. 64-68, 2017. [PDF]
32. B. S. Reniwala, Praneet Bhatiab and S. K. Vishvakarma, "Design and Investigation of Variability Aware Sense Amplifier for Low Power, High-Speed SRAM, " Microelectronics Journal, Elsevier, Vol. 59, pp. 22-32, Jan 2017. [PDF]
2016 (11)
31. Shamza Sheikh, S. K. Vishvakarma and B.S. Reniwal, "An Offset Compensated Sense Amplifier Based On Charge Storage Technique for SRAM," IEEE VLSI Circuits & Systems Letter, Vol. 2, Issue 2, October 2016. [PDF]
30. Deepika Gupta and S. K. Vishvakarma, “Impact of LDD depth variation on the performance characteristics of SONOS NAND flash memory device,” IEEE Transactions on Device and Materials and Reliability, 99, June 2016. [PDF]
29. Ankur Beohar and S. K. Vishvakarma, "Performance Enhancement of Asymmetrical Underlap 3D-Cylindrical GAA-TFET with Low Spacer Width, " IET Micro & Nano Letters, Vol. 11, issue 8, pp 443-445, August 2016. [PDF]
28. Mohit S. Choudhary, Mahesh Kumawat, Pramod K. Bharti and S. K. Vishvakarma, "16.64Gbps Synchronous CML SerDes Transceiver Design Technique with Process Corner Variations for Low Power Application, " IEEE VLSI Circuits & Systems Letter, Vol. 2, Issue 1, April 2016. [PDF]
27. C. B. Kushwah, S. K. Vishvakarma and D. Dwivedi, "A 20nm Robust Single-Ended Boost-Less 7T FinFET Sub-threshold SRAM Cell under Process-Voltage-Temperature Variation, "Microelectronics Journal, Elsevier, Vol. 51, pp. 75-88, May 2016. [PDF]
26. Deepika Gupta and S. K. Vishvakarma, "Improved Short Channel Characteristics with Long Data Retention time in Extreme Short Channel Flash Memory Devices, " IEEE Transactions on Electron Devices, issues 2, Vol. 63, pp. 668 - 674, Feb. 2016. [PDF]
25. C. B. Kushwah and S. K. Vishvakarma, "A Single-Ended with Dynamic Feedback Control 8T Sub-Threshold SRAM Cell", IEEE Transactions on Very Large Scale Integration (VLSI), Systems, issue 1, Vol. 24, pp. 373-377, Jan 2016. [PDF]
24. Vikas Vijayvargiya, Bhupendra Reniwal, Pooran Singh, S. K.Vishvakarma, "Analog/RF Performance Attributes of an Underlap Tunnel Field Effect Transistor for Low Power Applications, IET Electronics Letters, Vol. 52, issue 7, pp. 559-560, April 2016. [PDF]
23. Sonal Jain, Vaibhav Neema, Deepika Gupta, S. K. Vishvakarma, “Investigation of BE-SONOS Flash Memory with High-k Dielectrics in Tunnel Barrier and its Impact on Charge Retention Dynamics”, Journal of Nanoelectronics and Optoelectronics (JNO), vol. 11, No. 6, pp. 663-668, 2016. [PDF]
22.C. B. Kushwah, S. K. Vishvakarma and D. Dwivedi, “Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Cell Design in Sub-Threshold Regime for Ultra-Low Power Applications”, Circuits, Systems & Signal Processing (CSSP), Springer, no. 2, vol. 35, pp. 385-407, Feb. 2016. [PDF]
21. Sonal Jain, Deepika Gupta, Vaibhav Neema, S. K. Vishvakarma, “BE-SONOS Flash Memory along with Metal Gate and High-k Dielectrics in Tunnel Barrier and its Impact in Charge Retention Dynamics”, Journal of Semiconductors, IOPScience, Vo. 37, no. 3, March 2016. [PDF]
2015 (03)
20. Bhupendra Singh Reniwal, Vikas Vijayvargiya, S. K. Vishvakarma, Devesh Dwivedi, “Ultra-Fast Current Mode Sense Amplifier for Small ICELL SRAM in FinFET with Improved Offset Tolerance", Circuits, Systems & Signal Processing (CSSP), Springer, pp 1-20, Nov. 2015. [PDF]
19. C. B. Kushwah, S. K. Vishvakarma, and D. Dwivedi, “A boost-less write optimized single-ended robust 7T SRAM cell for ultra-low-power memory design”, International Journal of Electronics Letters (IJEL), Taylor Francis, Sept. 2015. [PDF]
18. Dheeraj Sharma and S. K. Vishvakarma, "Analyses of DC and Analog/RF Performances for Short Channel Quadruple-Gate gate-all-around MOSFET", Microelectronics Journal, Elsevier, vol. 46, issue 8, pp. 731-739-363, August 2015. [PDF]
2014 (01)
17. Vikas Vijaywargiya and S. K. Vishvakarma, "Effect of Drain Doping Profile on Double Gate Tunnel Field Effect Transistor and its Influence on Device RF Performance," IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 974- 981, Sept. 2014. [PDF]
2013 (05)
16. Dheeraj Sharma and S. K. Vishvakarma," Precise Analytical Model for Short Channel Quadruple gate-all-around MOSFET," IEEE Transactions on Nanotechnology, vol. 12, no. 3, pp. 378-385, May 2013. [PDF]
15. Bhupendra Reniwal and S. K. Vishvakarma, "A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultra Low power SRAM", International Journal of Electronics and Electrical Engineering, Canada, vol. 1, no. 1, March 2013. [PDF]
14. Pooran Singh and S. K. Vishvakarma," Device/Circuit/Architectural Techniques for Ultra Low power FPGA Design", Journal of Microelectronics and Solid-State Electronics, Scientific and Academic Publishing, USA, vol. 2, pp. 1-15, 2013. [PDF]
13. Dheeraj Sharma and S. K. Vishvakarma," Precise analytical model for short-channel Cylindrical Gate (CylG) Gate-ALL-Around (GAA) MOSFET” Solid-State Electronics, Elsevier, vol. 86, pp. 68-74, August 2013. [PDF]
12. Pooran Singh and S. K. Vishvakarma," FPGA Implementation of 413.121 MHz and 11.34 mW High-Speed Low Power Viterbi Decoder", IET International Journal of Modeling and Optimization, vol. 3, no. 1, February 2013. [PDF]
2012 (01)
11. Dheeraj Sharma and S. K. Vishvakarma, "Analytical Modeling of 3D Potential Distribution of a Rectangular Gate (RecG) Gate-All-around MOSFET in Subthreshold and Strong Inversion Regions "Microelectronics Journal, Elsevier, vol. 43, issue 6, pp. 358-363, June 2012. [PDF]
2011 (01)
10. S. K. Vishvakarma, V. Komal Kumar, A. K. Saxena and S. Dasgupta,"Modeling and Estimation of Edge Direct Tunneling Current for Nanoscale Metal Gate (Hf/AlNx) Symmetric Double-Gate MOSFET," Microelectronics Journal, Elsevier, vol. 42, issue 5, pp. 688-692, May 2011. [PDF]
2010 (03)
9. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Modeling and Estimation of Drain Current for Dual Metal Gate (Hf/AlNx) and Midgap Symmetric Double Gate (SDG) MOSFET, Journal of Computational and Theoretical Nanoscience (JCTN), vol. 7, no. 10, pp. 1941-1947, 2010. [PDF]
8. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Potential and Drain Current for Symmetric Double Gate (SDG) MOSFET using Self Consistent Solution of 1-D Poisson's Schrödinger Equations” Journal of Computational and Theoretical Nanoscience (JCTN), vol. 7, no. 10, pp. 1959-1964, 2010. [PDF]
7. V. Komal, S. K. Vishvakarma, R. C. Joshi, A. K. Saxena and S. Dasgupta, “Small Signal Capacitance and Glitch Power estimation of Nanoscale MGDG-MOSFET Based Circuits: A Device/Circuit Co-design Approach” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 5, no.1, pp. 72-78, 2010. [PDF]
2009 (02)
6. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Inversion Charge Density for Nanoscale Dual Metal Gate (Hf/AlNx) and Midgap Symmetric Double-Gate MOSFET” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 4, no. 3, pp. 370-379, 2009. [PDF]
5. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Symmetric Double Gate (SDG) MOSFET using 1D Schrödinger-Poisson Equation Solution” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 4, no. 3, pp. 353-361, 2009. [PDF]
2008 (02)
4. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Two Dimensional Analytical Potential Modeling of Nanoscale Fully Depleted Metal Gate Double Gate MOSFET,” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 3, no. 3, pp. 297-306, 2008. [PDF]
3. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “A Compact Drain Current and Threshold Voltage Quantum Mechanical Analytical Modeling for FinFETs,” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 3, no. 2, pp. 163-170, 2008. [PDF]
2007 (02)
2. S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta, “Modeling of Inversion Charge Density in Nanoscale Symmetric Double Gate (SDG) MOSFET: An analytical Approach,” Journal of Nanoelectronics and Optoelectronics (JNO), vol. 2, no. 3, pp. 287-293, 2007. [PDF]
1. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Nanoscale Double-Gate FinFET Device,” International Journal of Intelligent Electronics Systems, vol. 1. No. 1, pp. 66-71, 2007. [PDF]